A System-Level Timing Analysis and Optimization Methodology for Hardware Compilation

Electronic Design Automation (EDA) in the nano era faces a fresh set of challenges. Designs are getting larger and more complex, and design metrics are evolving from area and performance in the past to power and reliability in the future. In this changing landscape, the ITRS roadmap notes that it is imperative that we raise the level of abstraction in system-level design to deal with this increasing complexity, and look for reliable, manufacturing-friendly circuit architectures in order to overcome these challenges [1]. In my dissertation, I propose an optimization methodology based on system-level timing analysis, which can scale to large complex circuits. The system-level timing model allows the optimization phases to reason about global timing dependencies between circuit events [11], thereby enabling more efficient architectural design space exploration. Specifically, it computes a Global Critical Path (GCP), which traces a path through the circuit graph, indicating the most critical components in the execution. Unlike the traditional view of the critical path as an acyclic path between two clocked registers, the GCP is defined for the entire system, can cross register boundaries and can contain cycles. By computing the GCP, the optimization phases can then focus their efforts on the most important parts of the system, thus allowing us to handle large circuits without compromising efficiency, scalability or accuracy. This analysis and optimization methodology is depicted in Fig. 1, and has been incorporated into the CASH compiler (described below).